Designed a 16-bit array multiplier using carry save adders and drawing layout in Cadence. Improved performance of multiplier by pipelining multiplier using flip flops and latches.

HYDERABAD: Veda IIT based in Hyderabad is negotiating with Texas Instruments (TI), which has its R&D center in Bangalore, to get live projects for the students of Veda IIT to work with. Veda IIT is ...

A consortium of Gujarat-based education institutes has received Rs 3.84 crore from MeitY to develop and test VLSI technology. The five-year project aims to train faculty members and students in chip ...

Advanced Diploma In VLSI Design & TechnologyAdvanced Diploma in VLSI Design & Technology is an intensive course for enhancing and augmenting student’s knowledge in VLSI Design field. This course is ...