Static Timing Analysis using Cadence Tempus - Digital System Design
Static Timing Analysis using Cadence Tempus - Digital System Design
Jun 30, 2020
digitalsystemdesign.in
Discover how InspireSemi successfully taped out their Thunderbird Accelerated Computing chip at 12nm using Cadence's Digital Full Flow, achieving best-in-class PPA and on-time design closure. The integration of Cadence's Tempus Timing Solution and Quantus Extraction Solution significantly reduced signoff closure iterations, allowing them to meet their tight tapeout deadlines faster. With such positive results, InspireSemi is excited to continue leveraging the digital full flow for future project
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Discover how InspireSemi successfully taped out their Thunderbird Accelerated Computing chip at 12nm using Cadence's Digital Full Flow, achieving best-in-class PPA and on-time design closure. The integration of Cadence's Tempus Timing Solution and Quantus Extraction Solution significantly reduced signoff closure iterations, allowing them to meet their tight tapeout deadlines faster. With such positive results, InspireSemi is excited to continue leveraging the digital full flow for future project
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